Comparative de la tecnología electrónica convencional y la biológica: enfásis en la función de aprendizaje

En el presente proyecto, una vez realizado un amplio estudio sobre el sistema neuronal y su proceso de aprendizaje, se propone desarrollar diferentes algoritmos a partir de los cuales una máquina de estados finitos es capaz de aprender el comportamiento, parcial o completo, de un autómata externo. Este estudio puede servir como punto de partida para posteriores investigaciones acerca del sistema biológico y su posible aplicación al diseño de sistemas electrónicos, así como la evaluación de nuevas estrategias de diseño no orientado

Variability and reliability analysis of carbon nanotube technology in the presence of manufacturing imperfections

In 1925, Lilienfeld patented the basic principle of field effect transistor (FET). Thirty-four years later, Kahng and Atalla invented the MOSFET. Since that time, it has become the most widely used type of transistor in Integrated Circuits (ICs) and then the most important device in the electronics industry. Progress in the field for at least the last 40 years has followed an exponential behavior in accordance with Moore¿s Law. That is, in order to achieve higher densities and performance at lower power consumption, MOS devices have been scaled down. But this aggressive scaling down of the physical dimensions of MOSFETs has required the introduction of a wide variety of innovative factors to ensure that they could still be properly manufactured. Transistors have expe- rienced an amazing journey in the last 10 years starting with strained channel CMOS transistors at 90nm, carrying on the introduction of the high-k/metal-gate silicon CMOS transistors at 45nm until the use of the multiple-gate transistor architectures at 22nm and at recently achieved 14nm technology node. But, what technology will be able to produce sub-10nm transistors? Different novel materials and devices are being investigated. As an extension and enhancement to current MOSFETs some promising devices are n-type III-V and p-type Germanium FETs, Nanowire and Tunnel FETs, Graphene FETs and Carbon Nanotube FETs. Also, non-conventional FETs and other charge-based information carrier devices and alternative information processing devices are being studied. This thesis is focused on carbon nanotube technology as a possible option for sub-10nm transistors. In recent years, carbon nanotubes (CNTs) have been attracting considerable attention in the field of nanotechnology. They are considered to be a promising substitute for silicon channel because of their small size, unusual geometry (1D structure), and extraordinary electronic properties, including excellent carrier mobility and quasi-ballistic transport. In the same way, carbon nanotube field-effect transistors (CNFETs) could be potential substitutes for MOSFETs. Ideal CNFETs (meaning all CNTs in the transistor behave as semiconductors, have the same diameter and doping level, and are aligned and well-positioned) are predicted to be 5x faster than silicon CMOS, while consuming the same power. However, nowadays CNFETs are also affected by manufacturing variability, and several significant challenges must be overcome before these benefits can be achieved. Certain CNFET manufacturing imperfections, such as CNT diameter and doping variations, mispositioned and misaligned CNTs, high metal-CNT contact resistance, the presence of metallic CNTs (m-CNTs), and CNT density variations, can affect CNFET performance and reliability and must be addressed. The main objective of this thesis is to analyze the impact of the current CNFET manufacturing challenges on multi-channel CNFET performance from the point of view of variability and reliability and at different levels, device and circuit level. Assuming that CNFETs are not ideal or non-homogeneous because of today CNFET manufacturing imperfections, we propose a methodology of analysis that based on a CNFET ideal compact model is able to simulate heterogeneous or non-ideal CNFETs; that is, transistors with different number of tubes that have different diameters, are not uniformly spaced, have different source/drain doping levels, and, most importantly, are made up not only of semiconducting CNTs but also metallic ones. This method will allow us to analyze how CNT-specific variations affect CNFET device characteristics and parameters and CNFET digital circuit performance. Furthermore, we also derive a CNFET failure model and propose an alternative technique based on fault-tolerant architectures to deal with the presence of m-CNTs, one of the main causes of failure in CNFET circuits

Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm

3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability.Peer ReviewedPostprint (author's final draft

Code deformation and lattice surgery are gauge fixing

International audienceThe large-scale execution of quantum algorithms requires basic quantum operations to be implemented fault-tolerantly. The most popular technique for accomplishing this, using the devices that can be realized in the near term, uses stabilizer codes which can be embedded in a planar layout. The set of fault-tolerant operations which can be executed in these systems using unitary gates is typically very limited. This has driven the development of measurement-based schemes for performing logical operations in these codes, known as lattice surgery and code deformation. In parallel, gauge fixing has emerged as a measurement-based method for performing universal gate sets in subsystem stabilizer codes. In this work, we show that lattice surgery and code deformation can be expressed as special cases of gauge fixing, permitting a simple and rigorous test for fault-tolerance together with simple guiding principles for the implementation of these operations. We demonstrate the accuracy of this method numerically with examples based on the surface code, some of which are novel

Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm

Best DCIS Paper Award 20123T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability.Peer ReviewedAward-winningPreprin

Comparative de la tecnología electrónica convencional y la biológica: enfásis en la función de aprendizaje

En el presente proyecto, una vez realizado un amplio estudio sobre el sistema neuronal y su proceso de aprendizaje, se propone desarrollar diferentes algoritmos a partir de los cuales una máquina de estados finitos es capaz de aprender el comportamiento, parcial o completo, de un autómata externo. Este estudio puede servir como punto de partida para posteriores investigaciones acerca del sistema biológico y su posible aplicación al diseño de sistemas electrónicos, así como la evaluación de nuevas estrategias de diseño no orientado

Comparative de la tecnología electrónica convencional y la biológica: enfásis en la función de aprendizaje

En el presente proyecto, una vez realizado un amplio estudio sobre el sistema neuronal y su proceso de aprendizaje, se propone desarrollar diferentes algoritmos a partir de los cuales una máquina de estados finitos es capaz de aprender el comportamiento, parcial o completo, de un autómata externo. Este estudio puede servir como punto de partida para posteriores investigaciones acerca del sistema biológico y su posible aplicación al diseño de sistemas electrónicos, así como la evaluación de nuevas estrategias de diseño no orientado

A comparative variability analysis for CMOS and CNFET 6T SRAM cells

Statistical device variability may be a limiting factor for further miniaturizing nodes in silicon bulk CMOS technology. On the other hand, in novel technologies such as Carbon Nanotubes Field Effect Transistors (CNFETs), the device variability is also present and is mainly due to imperfections inherent in current carbon nanotube (CNT) growth methods. The goal of this paper is to evaluate the impact of the main sources of variability in conventional MOSFET and CNFET 6T SRAM cells through the consideration of random threshold voltage process variations.Peer Reviewe

Carbon nanotube growth process-related variablity in CNFET's

In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. Novel nanoscale beyond- CMOS devices are being studied such as carbon nanotubes (CNTs). The goal of this paper is to evaluate the parameter variability in Carbon Nanotube Field Effect Transistors (CNFETs) and their potential capability to be a promising alternative to Si-CMOS technology.Peer Reviewe

Carbon nanotube growth process-related variablity in CNFET's

In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. Novel nanoscale beyond- CMOS devices are being studied such as carbon nanotubes (CNTs). The goal of this paper is to evaluate the parameter variability in Carbon Nanotube Field Effect Transistors (CNFETs) and their potential capability to be a promising alternative to Si-CMOS technology.Peer ReviewedPostprint (published version